• DocumentCode
    903030
  • Title

    Noise-generation analysis and noise-suppression design techniques in megabit DRAMs

  • Author

    Itoh, Y. ; Nakagawa, K. ; Sakui, K. ; Horiguchi, F. ; Ogura, M.

  • Volume
    22
  • Issue
    4
  • fYear
    1987
  • fDate
    8/1/1987 12:00:00 AM
  • Firstpage
    619
  • Lastpage
    622
  • Abstract
    A detailed noise-generation model of peak current and voltage-bouncing noise for DRAMs is presented. This model was found to be a very effective tool for predicting and analyzing quantitative bouncing noise level in noise-suppress circuit design, especially for high-performance high-density DRAMs. The resulting performance for the fabricated NMOS 1-Mb DRAM is 100-mA peak current, 6-mA/ns current transition rate, and 0.27-V output voltage-bouncing noise for a standard system board.
  • Keywords
    Electron device noise; Field effect integrated circuits; Integrated memory circuits; Interference suppression; Random-access storage; electron device noise; field effect integrated circuits; integrated memory circuits; interference suppression; random-access storage; BiCMOS integrated circuits; Circuit noise; Circuit synthesis; MOS devices; Noise level; Random access memory; Solid state circuit design; Solid state circuits; Very large scale integration; Voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1987.1052782
  • Filename
    1052782
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=903030