DocumentCode
903373
Title
Characteristics of a set of 12.7-mm processor chips
Author
Klein, Klaus ; Koetzle, Gunther ; Miersch, Ekkehard F. ; Schettler, Helmut ; Schulz, Uwe ; Wagner, Otto
Volume
22
Issue
5
fYear
1987
fDate
10/1/1987 12:00:00 AM
Firstpage
783
Lastpage
789
Abstract
A 1.0-μm CMOS technology with three layers of metal is used to implement a high-density master image that contains logic and RAMs. The image allows the use of more than 1,000,000 transistors. A hierarchical design methodology is described. This chip offers variable-sized physical partitions and RAM macros. Fixed area sizes and locations for partitions and macros are not necessary. Density and performance of custom chips are approached by the described methodology with significantly lower development cost and time.
Keywords
CMOS integrated circuits; Circuit layout CAD; Logic CAD; Microprocessor chips; VLSI; circuit layout CAD; logic CAD; microprocessor chips; CMOS logic circuits; CMOS process; CMOS technology; Integrated circuit technology; Laboratories; Logic circuits; Power distribution; Read-write memory; Very large scale integration; Wiring;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052814
Filename
1052814
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