DocumentCode
903402
Title
A 553 K-transistor LISP processor chip
Author
Bosshart, Patrick W. ; Hewes, C. Robert ; Ales, Michael D. ; Chang, Mi-Chang ; Chau, Kwok Kit ; Fasham, Kingsley ; Hoac, Charles C. ; Houston, Theodore W. ; Kalyan, Vibhu ; Lusky, Stephen L. ; Mahant-Shetti, Shivaling S. ; Matzke, Douglas J. ; Ruparel, Ka
Volume
22
Issue
5
fYear
1987
fDate
10/1/1987 12:00:00 AM
Firstpage
808
Lastpage
819
Abstract
The authors describe a LISP microprocessor which includes over 550 K transistors, has 114 K of on-chip RAM, and runs instructions in a single 30-ns clock cycle. The chip is implemented in 1.25-μm double-level-metal (DLM) CMOS, has 224 pins, and is packaged in a custom pin-grid array. The microinstruction and macroinstruction sets of this chip are compatible with an existing LISP processor. An extensive discussion of test features designed into the processor chip is given.
Keywords
Automatic testing; CMOS integrated circuits; LISP; Microprocessor chips; Pipeline processing; VLSI; automatic testing; microprocessor chips; pipeline processing; Clocks; Computer architecture; Instruments; Microprocessors; Packaging; Pins; Pipelines; Process design; Read-write memory; Senior members;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052817
Filename
1052817
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