DocumentCode
903503
Title
Selector-line merged built-in ECC technique for DRAMs
Author
Yamada, Junzo
Volume
22
Issue
5
fYear
1987
fDate
10/1/1987 12:00:00 AM
Firstpage
868
Lastpage
873
Abstract
A high-performance built-in error checking and correcting (ECC) technique applicable to megabit-level dynamic RAM (DRAM) chips is described. This technique, based on a bidirectional parity code, achieves high-speed error correction with a minimum increase in area. The impact of the technique on access time and chip overhead is discussed. Furthermore, effects on soft-error reduction and yield improvement are analytically investigated.
Keywords
Error correction; Error detection; Integrated memory circuits; Random-access storage; error correction; error detection; integrated memory circuits; random-access storage; DRAM chips; Error analysis; Error correction; Error correction codes; Fabrication; Helium; Integrated circuit technology; Integrated circuit yield; Redundancy; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052826
Filename
1052826
Link To Document