DocumentCode
903520
Title
CMOS scan-path IC design for stuck-open fault testability
Author
Liu, Dick L. ; McCluskey, Edward J.
Volume
22
Issue
5
fYear
1987
fDate
10/1/1987 12:00:00 AM
Firstpage
880
Lastpage
885
Abstract
A design technique which facilitates testing for stuck-open faults in CMOS VLSI circuits with scan paths is described. In this technique, the combinational circuitry is implemented with specially designed gates which can be tested with a simplified two-pattern test for stuck-open faults. The simplified two-pattern test cannot be invalidated by stray circuit delays and it can be applied through the scan path by specially designed shift-register latches (SRLs).
Keywords
CMOS integrated circuits; Combinatorial circuits; Integrated circuit testing; Integrated logic circuits; Logic design; Logic testing; VLSI; combinatorial circuits; integrated circuit testing; integrated logic circuits; logic design; logic testing; CMOS integrated circuits; Circuit faults; Circuit testing; Combinational circuits; Delay; FETs; Integrated circuit testing; Logic gates; Robustness; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052828
Filename
1052828
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