DocumentCode
904281
Title
Low-cost associative memory
Author
Mundy, Joseph L. ; Burgess, James F. ; Joynson, Reuben E. ; Neugebauer, Constantine
Volume
7
Issue
5
fYear
1972
fDate
10/1/1972 12:00:00 AM
Firstpage
364
Lastpage
369
Abstract
The authors describe the design of two high-density MOS associative memory cells. The first cell is suitable for data management applications, having three internal states including the DON´T CARE (mask) condition. The second cell is suitable for parallel processing applications and has the capability of selected bit writing. Both cells consume about 20 mil/SUP 2/ of silicon area, which allows the implementation of 512 bits on a chip. Varactor bootstrapping is used to enhance the storage node voltage for improved cell operation. The use of a compatible bipolar transistor is discussed.
Keywords
Associative storage; Economics; Metal-insulator-semiconductor devices; Semiconductor storage devices; associative storage; economics; metal-insulator-semiconductor devices; semiconductor storage devices; Associative memory; Circuits; Costs; Large scale integration; Logic arrays; Parallel processing; Random access memory; Silicon; Varactors; Writing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1972.1052894
Filename
1052894
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