A flexible 128 channel silicon strip detector instrumentation integrated circuit with sparse data readout

A full-custom CMOS integrated circuit for silicon strip detector systems has been designed, fabricated, and tested. The circuit contains 128 parallel data-acquisition channels and considerable peripheral circuitry. Each channel consists of a low-noise, low-power, charge-sensitive amplifier, a multistage autobalanced comparator, an analog multiplexer, nearest-neighbor logic, priority-search logic, and a share of a position-encoding read-only memory. The analog system can substract both detector pedestal and leakage current on a channel-by-channel basis. A key feature of this design is the inclusion of on-chip sparse read-out circuitry, which allows efficient management of low-occupancy events. Designed for use at the Collider Detector Facility (CDF) at Fermilab, the circuit is suitable for large-scale silicon detector systems requiring a large, dense array of fast, low-power electronics.<>