Detection of catastrophic faults in analog integrated circuits

Author

Milor, Linda ; Visvanathan, V.

Author_Institution

Dept. of Electr. Eng., California Univ., Berkeley, CA, USA

Volume

8

Issue

2

fYear

1989

fDate

2/1/1989 12:00:00 AM

Firstpage

114

Lastpage

130

Abstract

The IC fabrication process contains several testing stages. Because of the high cost of packaging, the testing stage prior to aging, called wafer probe, is key in reducing the overall manufacturing cost. Typically in this stage, specification tests are performed. Even though specification tests can certainly distinguish a good circuit from all faulty ones, they are expensive, and many types of faulty behavior can be detected by simpler tests. The construction of a set of measurements that detects many faulty circuits before specification testing is described. Bounds on these measurements are specified, and an algorithm for test selection is presented. An example of a possible simple test is a test of DC voltages (i.e., parametric tests). This type of test is defined rigorously, and its effectiveness in detecting faulty circuits is evaluated

Keywords

analogue circuits; fault location; integrated circuit testing; linear integrated circuits; production testing; DC voltages; IC fabrication process; analog integrated circuits; catastrophic faults; manufacturing cost; parametric tests; specification tests; testing stage; wafer probe; Aging; Analog integrated circuits; Circuit faults; Circuit testing; Costs; Electrical fault detection; Fabrication; Fault detection; Integrated circuit packaging; Integrated circuit testing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.21830

Filename

21830