• DocumentCode
    911951
  • Title

    Modeling Latch-Up in CMOS Integrated Circuits

  • Author

    Estreich, Donald B. ; Dutton, Robert W.

  • Author_Institution
    Hewlett-Packard Company, Santa Rosa, CA, USA
  • Volume
    1
  • Issue
    4
  • fYear
    1982
  • fDate
    10/1/1982 12:00:00 AM
  • Firstpage
    157
  • Lastpage
    162
  • Abstract
    Latch-up is a common problem in CMOS integrated circuits. The modeling of latch-up with circuit simulation programs is addressed in this paper. The general features of a lumped element latch-up model are discussed along with a step-by-step approach to the component determination of the model. An example is presented to show the value of the latch-up model in latch-up threshold prediction. Finally, some latch-up control methods are discussed.
  • Keywords
    CMOS integrated circuits; Equivalent circuits; Integrated circuit modeling; Inverters; Ionizing radiation; Latches; Physics; Predictive models; Semiconductor device modeling; Voltage;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1982.1270006
  • Filename
    1270006
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=911951