DocumentCode
912780
Title
Signal Delay in General RC Networks
Author
Lin, Tzu-Mu ; Mead, Carver A.
Author_Institution
Department of Computer Science, California Institute of Technology, Pasadena, CA, USA
Volume
3
Issue
4
fYear
1984
fDate
10/1/1984 12:00:00 AM
Firstpage
331
Lastpage
349
Abstract
Based upon the delay of Elmore, a single value of delay is derived for any node in a general RC network. The effects of parallel connections and stored charge are properly taken into consideration. A technique called tree decomposition and load redistribution is introduced that is capable of dealing with general RC networks without sacrificing a number of desirable properties of tree networks. An experimental simulator called SDS (Signal Delay Simulator) has been developed. For all the examples tested so far, this simulator runs two to three orders of magnitude faster than SPICE, and detects all transitions and glitches at approximately the correct time.
Keywords
Biographies; Circuit simulation; Circuit testing; Computer science; Delay effects; Delay estimation; Equations; Intelligent networks; MOSFETs; SPICE;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.1984.1270090
Filename
1270090
Link To Document