• DocumentCode
    914268
  • Title

    A Fast-Timing Simulator for Digital MOS Circuits

  • Author

    Tsao, David ; Chen, Chinu-fu

  • Author_Institution
    AT&T Bell Laboratories, Murray Hill, NJ, USA
  • Volume
    5
  • Issue
    4
  • fYear
    1986
  • fDate
    10/1/1986 12:00:00 AM
  • Firstpage
    536
  • Lastpage
    540
  • Abstract
    An efficient and accurate algorithm has been developed for predicting the timing waveforms of general MOS transistor circuits. The algorithm uses a switch-level simulation technique to determine the steady-state conditions, a forward prediction method to predict the transient time between two adjacent voltage levels, a simplified timing simulation technique to correct this delay, and novel approaches for controlling the voltage step automatically. The simulation is further speeded up by the use of a table lookup model to calculate the transistor current and macromodels to evaluate certain circuit structures. This algorithm has been implemented as a new simulation mode, called fast timing, in the MOTIS3 multilevel mixed-mode simulator. Many production chips have been verified, and the results show that the fast-timing simulation can be three orders of magnitude faster than a conventional circuit analysis program such as SPICE, one order of magnitude faster than the MOTIS3 timing simulation, and only five times slower than the MOTIS3 unit-delay, switch-level evaluator. The delay accuracy of the new simulator is within 5 percent of the timing simulation.
  • Keywords
    Analytical models; Automatic voltage control; Circuit simulation; Delay effects; MOSFETs; Prediction methods; Predictive models; Steady-state; Table lookup; Timing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1986.1270224
  • Filename
    1270224