CMOS Hamming net with digital decoding capability and memory

The digital decoding and memory features for a CMOS 2 mu m n-well technology Hamming net by PSpice simulation are presented. This analogue parallel net that processes input binary patterns is supported by a nonlinear and self-excitatory mechanism, whose silicon implementation is low in complexity. This idea is applied to early current-mode competing WTA units, observing that their analogue nature to select the ´winner´ is changed by a digital behaviour. Moreover, the winning and losing WTA units keep their current digital state independent from further input patterns.