DocumentCode

917456

Title

Design of frequency-mode set-valued logic networks

Author

Aoki, Toyohiro ; Yuminaka, Yasushi ; Higuchi, Tatsuro

Volume

140

Issue

3

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

191

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings G

Publisher

iet

ISSN

0956-3768

Type

jour

Filename

221156