Hot-carrier degradation of single-drain PMOSFETs with differing sidewall spacer thicknesses

The effect of the sidewall spacer thickness on the hot-carrier degradation of buried-channel PMOS transistors with a sidewall-offset single drain structure was studied. At the bias stress condition of maximum gate current, a large degradation was observed for transistors with no overlap between gate and drain. Results of measurements using the charge-pumping technique suggest that trapping of a large number of electrons in the CVD SiO/sub 2/ sidewall spacer is responsible for the enhanced degradation. This was also confirmed by the measurement of the threshold voltage as a function of drain bias.<>