A CMOS low-distortion fully differential power amplifier with double nested Miller compensation

Author

Pernici, Sergio ; Nicollini, Germano ; Castello, Rinaldo

Author_Institution

ST SGS-Thomson Microelectron., Agrate Brianza, Italy

Volume

28

Issue

7

fYear

1993

fDate

7/1/1993 12:00:00 AM

Firstpage

758

Lastpage

763

Abstract

A four-stage fully differential power amplifier using a double-nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and stability conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and total harmonic distortion (THD) is -83 dB for a -V_p-p differential output signal at 10 kHz and a load of 50 Ω. With an 8 Ω load and for a 10-kHz, 4-V _p-p output signal, THD is -68 dB. The chip area is 0.625 mm ² in a 1.5-μm single-poly, double-metal, n-well CMOS technology

Keywords

CMOS integrated circuits; compensation; differential amplifiers; electric distortion; feedback; linear integrated circuits; power amplifiers; stability; 1.5 micron; 10 mW; 3 to 5 V; THD; design criteria; double nested Miller compensation; double-metal; four-stage; fully differential power amplifier; low-distortion; monolithic IC; multiple-loop configuration; n-well CMOS technology; single-poly; stability conditions; total harmonic distortion; Acoustic distortion; CMOS technology; Differential amplifiers; Linearity; Power amplifiers; Power dissipation; Power supplies; Silicon; Stability; Topology;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.222173

Filename

222173