On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L_min≈4.5(t_Si+(ε_Si/ε_I)t_I), where t_Si is the silicon thickness, and ε_I and t_I are the permittivity and thickness of the gate insulator. With t_Si limited to ≥ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L_min=20 nm is projected for oxides, and L_min=10 nm for high-κ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.