DocumentCode
919746
Title
Device enhancement using process-strained-Si for sub-100-nm nMOSFET
Author
Wang, Jen-Pan ; Su, Yan-Kuin ; Chen, Jone F.
Author_Institution
Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan
Volume
53
Issue
5
fYear
2006
fDate
5/1/2006 12:00:00 AM
Firstpage
1276
Lastpage
1279
Abstract
Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6 μm for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917 μA/μm for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.
Keywords
MOSFET; elemental semiconductors; etching; oscillators; silicon; 0.6 micron; 1.2 V; 1.7 nm; 80 nm; Si; bulk nMOSFET; gate delay; high-tensile contact etch stop layer; inverter ring oscillator; pMOSFET performance; process-strained-silicon; CMOS technology; Capacitive sensors; Degradation; Electron mobility; Etching; Geometry; MOS devices; MOSFET circuits; Stress; Tensile strain; Contact etch stop layer; mobility; strain; sub-100-nm nMOSFET;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2006.871874
Filename
1624715
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