Completely iterative, pipelined multiplier array suitable for VLSI

A pipelined array multiplier which has been derived by applying `systolic array¿ principles at the bit level is described. Initially, attention is focused on a circuit which is used to multiply streams of parallel unsigned data. We then give details of an algorithm which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two´s complement numbers. The resulting structure has a number of features which make it extremely attractive to LSI and VLSI. These include regularity and modularity.