A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture

Author

Tanoi, Satoru ; Tanabe, Tetsuya ; Takahashi, Kazuhiko ; Miyamoto, Sanpei ; Uesugi, Masaru

Author_Institution

OKI Electr. Ind. Co. Ltd., Tokyo, Japan

Volume

31

Issue

4

fYear

1996

fDate

4/1/1996 12:00:00 AM

Firstpage

487

Lastpage

493

Abstract

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-μm CMOS technology is used to fabricate the chip

Keywords

CMOS digital integrated circuits; buffer circuits; clocks; delay circuits; flip-flops; jitter; 0.4 micron; 150 ns; 250 to 622 MHz; 40 ps; CMOS technology; acquisition time; current-mode phase detector; delay-locked loop; flip-flop metastability; frequency-locked loop; jitter-suppressed clock buffer; operating frequency range; reference frequency supply; two-loop architecture; CMOS technology; Clocks; Delay; Detectors; Flip-flops; Frequency locked loops; Frequency measurement; Metastasis; Phase detection; Semiconductor device measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.499724

Filename

499724