A current direction sense technique for multiport SRAM´s

Author

Izumikawa, Masanori ; Yamashina, Masakazu

Author_Institution

Syst. ULSI Res. Lab., NEC Corp., Kanagawa, Japan

Volume

31

Issue

4

fYear

1996

fDate

4/1/1996 12:00:00 AM

Firstpage

546

Lastpage

551

Abstract

This paper describes two techniques for low-power single-end multiport SRAMs: a current direction sense circuit and a write bit-line swing control circuit. The sense circuit´s input node is clamped at an intermediate voltage level, and the circuit transforms current direction into a logic value. It operates four times faster than a CMOS inverter, when driver sizes are equal, When it is applied to a single-end multiport SRAM, access is accelerated 3.2 times faster than that with a CMOS inverter with no increase in power consumption. The write bit-line swing control circuit reduces the bit-line precharge level within the limit of correct operation by using a memory cell replica. The control circuit reduces power consumption for bit-line driving and pseudoread cell current by 40%

Keywords

CMOS memory circuits; SRAM chips; bit-line precharge level; current direction sense technique; low-power single-ended SRAM; memory cell replica; multiport SRAM; power consumption reduction; write bit-line swing control circuit; Acceleration; CMOS logic circuits; CMOS memory circuits; CMOS technology; Differential amplifiers; Driver circuits; Energy consumption; Inverters; Logic circuits; Random access memory; Registers; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.499731

Filename

499731