DocumentCode
921330
Title
Tolerance design via cost minimisation
Author
Maratos, N.
Author_Institution
Imperial College of Science & Technology, Department of Electrical Engineering, London, UK
Volume
129
Issue
4
fYear
1982
fDate
8/1/1982 12:00:00 AM
Firstpage
150
Lastpage
159
Abstract
A new method is described for the tolerance design of circuits, via minimisation of a cost function of the yield and tolerances. This problem is decomposed into the simpler problems of design centring with fixed tolerances, and tolerance assignment by efficient nonlinear optimisation based on a nonlinear approximation of the yield/tolerance dependence. Two algorithms are proposed, and their performance is evaluated on numerical examples.
Keywords
minimisation; network synthesis; circuit design; cost minimisation; design centering; efficient nonlinear optimisation; network synthesis; tolerance assignment; tolerance design; yield; yield/tolerance dependence;
fLanguage
English
Journal_Title
Electronic Circuits and Systems, IEE Proceedings G
Publisher
iet
ISSN
0143-7089
Type
jour
DOI
10.1049/ip-g-1:19820028
Filename
4645330
Link To Document