Measuring and utilising the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks

As the logic capacity of field-programmable gate arrays (FPGAs) increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of conventional logic blocks, FPGAs can now include digital signal processors, multipliers, multi-bit addressable memory cells and even processor cores. One of the common characteristics of these new building blocks is their multi-bit design, where each block is designed specifically to process several bits of data at a time. This multi-bit processing paradigm is significantly different from the single-bit processing design of the conventional FPGA logic blocks, as it creates differentiation in signals through its bussed structures. Consequently, the correlation between the positions of the signals in buses and the connectivity of these signals is examined. On the basis of correlation measurements, a multi-bit routing architecture is then proposed along with its routing tool. It is experimentally shown that, compared with the conventional routing architectures, the multi-bit architecture requires 6-12% less area to implement. In particular, it needs 27% fewer routing switches to connect its multi-bit blocks to their routing tracks and 18% less configuration memory to store the configuration information.