DocumentCode
928674
Title
An algorithm for the partitioning of logic circuits
Author
Roberts, M.W. ; Lala, P.K.
Author_Institution
University of York, Department of Computer Science, York, UK
Volume
131
Issue
4
fYear
1984
fDate
7/1/1984 12:00:00 AM
Firstpage
113
Lastpage
118
Abstract
The exhaustive testing of today´s digital circuits is not possible, owing to the vast test sequences which would have to be applied. Breaking down the circuit into manageable subcircuits (partitioning) makes exhaustive testing practicable. Partitioning has previously been done by the designer of the circuit in rather an ad hoc manner. The paper describes an algorithm which can be used to find the partitioning points in a circuit. The algorithm is illustrated for circuits containing reconvergent and nonreconvergent fan-outs.
Keywords
logic circuits; logic testing; digital circuits; exhaustive testing; logic circuits; nonreconvergent fan-outs; partitioning algorithm; reconvergent fan-outs; test sequences;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings E
Publisher
iet
ISSN
0143-7062
Type
jour
DOI
10.1049/ip-e.1984.0021
Filename
4646102
Link To Document