Switch-level timing simulation of bipolar ECL circuits

A method for switch-level timing simulation of bipolar emitter-coupled-logic (ECL) circuits is presented. The approach is based on the development of a switch level model of the transistor and on the representation of the circuit by a switch-graph. The circuit is partitioned into subcircuits, and the symbolic logic expressions, which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions, are then generated. Timing information is computed using a new physical delay model based on device equations, transistor interconnection, input slew rate, and loading conditions. The delay model was derived on the basis of average branch current analysis and incorporates more than 15 delay-sensitive circuit and SPICE BJT model parameters. The use of a novel parametric correction scheme permits greater freedom to handle complex effects such as high-level injection, parasitic resistances, and interconnection delay. In addition, the dynamic fanout effects due to base leakage current are incorporated by a fanout collapsing technique