• DocumentCode
    930911
  • Title

    A 10-bit 20-MHz two-step parallel A/D converter with internal S/H

  • Author

    Shimizu, Toshihiko ; Hotta, Masao ; Maio, Kenji ; Ueda, Seiichi

  • Author_Institution
    Central Res. Lab., Hitachi Ltd., Tokyo, Japan
  • Volume
    24
  • Issue
    1
  • fYear
    1989
  • Firstpage
    13
  • Lastpage
    20
  • Abstract
    A 10-bit 20-MHz A/D converter for high-quality video systems such as high-definition television, video tape recorders for business use, and digital video cameras is described. This LSI circuit uses a standard two-step parallel architecture, includes automatic gain adjustment and digital two-bit error correction, and has a sample-and-hold circuit on the chip. It is fabricated by a 4.5-GHz f/sub T/. 3- mu m-rule standard bipolar technology. Its die size is 25 mm/sup 2/, and its power consumption is 900 mW, which is about half of the lowest values reported to date. The converter can digitize video signals of up to 8.5 MHz at a conversion frequency of 20 MHz. The error in differential gain is 0.5 percent, and the error in differential phase is 0.5 degrees .<>
  • Keywords
    analogue-digital conversion; bipolar integrated circuits; large scale integration; video equipment; 20 MHz; 3 micron; 5 mm; 8.5 MHz; 900 mW; LSI circuit; automatic gain adjustment; bipolar technology; conversion frequency; die size; digital video cameras; error in differential gain; error in differential phase; high-definition television; high-quality video systems; power consumption; sample-and-hold circuit; two-bit error correction; two-step parallel architecture; video ADC; video tape recorders; Circuits; Digital cameras; Energy consumption; Error correction; Frequency conversion; HDTV; High definition video; Large scale integration; Parallel architectures; TV;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.16296
  • Filename
    16296