A 32 K ASIC synchronous RAM using a two-transistor basic cell

Author

Yuen, Alex ; Tsao, Peter ; Yin, Patrick ; Yuen, Albert T.

Author_Institution

LSI Logic Corp., Milpitas, CA, USA

Volume

24

Issue

1

fYear

1989

Firstpage

57

Lastpage

61

Abstract

A 32 K synchronous RAM using a two-transistor basic cell has been developed for use with a 100 K compact gate array. The basic cell consists of only two transfer gates and a storage capacitor and thus results in a very dense memory array. The RAM operates as a static RAM during system operations and provides both serial and parallel data ports. It can be reconfigured into 1 K*32, 2 K*16, 4 K*8, etc. depending on the system needs. An access time of 40 ns was achieved for a test chip at an operating power of 175 mW.<>

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; integrated circuit technology; integrated memory circuits; logic arrays; random-access storage; 100 K compact gate array; 175 mW; 2 T cell; 32 K synchronous RAM; 32 kbit; 4 ns; ASIC; CMOS; HCMOS; access time; dense memory array; operating power; parallel data ports; reconfigurable; serial data ports; static RAM; storage capacitor; system operations; test chip; two-transistor basic cell; Application specific integrated circuits; Capacitance; Capacitors; Degradation; Delay; Latches; Random access memory; Read-write memory; Testing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.16302

Filename

16302