Eliminating the fanout bottleneck in parallel long BCH encoders

Author

Parhi, Keshab K.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA

Volume

51

Issue

3

fYear

2004

fDate

3/1/2004 12:00:00 AM

Firstpage

512

Lastpage

516

Abstract

Long BCH codes can achieve about 0.6-dB additional coding gain over Reed-Solomon codes with similar code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fanout, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. In this paper, a novel scheme based on look-ahead computation and retiming is proposed to eliminate the effect of large fanout in parallel long BCH encoders. For a (2047, 1926) code, compared to the original parallel BCH encoder architecture, the modified architecture can achieve a speedup of 132%.

Keywords

BCH codes; optical communication; shift registers; Reed-Solomon codes; clock speed; coding gain; data rate requirement; fanout bottleneck; linear feedback shift register architecture; long-haul optical communication systems; look-ahead computation; look-ahead retiming; parallel long BCH encoders; AWGN; Clocks; Computer architecture; Concurrent computing; Delay; Encoding; Linear feedback shift registers; Optical fiber communication; Parallel processing; Polynomials;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2004.823655

Filename

1275598