• DocumentCode
    932339
  • Title

    Experiment to investigate self-testing techniques in VLSI

  • Author

    Williams, T.W. ; Walther, R.G. ; Bottorff, P.S. ; Das Gupta, S.

  • Author_Institution
    International Business Machines Corporation, Boulder, USA
  • Volume
    132
  • Issue
    3
  • fYear
    1985
  • fDate
    6/1/1985 12:00:00 AM
  • Firstpage
    105
  • Lastpage
    107
  • Abstract
    The paper contains the results of an experiment which observes the capabilities of a linear feedback shift register network, to both generate pseudorandom test patterns and compress the results of a test. Two typical networks from an actual LSI designed machine are used.
  • Keywords
    VLSI; integrated circuit testing; logic testing; IC testing; LSI designed machine; VLSI; combinational networks; linear feedback shift register network; logic circuits; pattern generation; pseudorandom test patterns; self-testing techniques;
  • fLanguage
    English
  • Journal_Title
    Electronic Circuits and Systems, IEE Proceedings G
  • Publisher
    iet
  • ISSN
    0143-7089
  • Type

    jour

  • DOI
    10.1049/ip-g-1:19850022
  • Filename
    4646484
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=932339