DocumentCode
932694
Title
Efficient improvement of hot carrier-induced degradation for 0.1-μm indium-halo nMOSFET
Author
Yeh, Wen-Kuan ; Lin, Jung-Chun
Author_Institution
Dept. of Electr. Eng., Nat. Univ. of Kaohsiung, Taiwan
Volume
51
Issue
4
fYear
2004
fDate
4/1/2004 12:00:00 AM
Firstpage
642
Lastpage
644
Abstract
The effect of post-thermal annealing after indium-halo implantation on the reliability of sub-0.1-μm nMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures (e.g., 900°C) for a longer time.
Keywords
MOSFET; annealing; hot carriers; indium; leakage currents; semiconductor device breakdown; surface states; MOSFET reliability; annealing temperature; annealing time control; device performance; hot carrier-induced degradation; hot carrier-induced device degradation; indium-halo implantation; indium-halo nMOSFET; post-annealing treatment; post-thermal annealing; Annealing; CMOS technology; CMOSFETs; Degradation; Indium; Ion implantation; MOSFET circuits; Manufacturing; Temperature control; Threshold voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2004.823797
Filename
1275652
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