Modelling compelled multiprocessor systems

The paper presents a method of predicting the performance, in terms of throughput, of multiprocessor systems in which the processes are not dynamically reconfigurable. The analysis is restricted to a type of system which is referred to as compelled, meaning that a user must wait for the system´s response before sending additional data. The analysis provides a method for predicting the throughput characteristics of the system and also considers the case where more than one processor can do a particular part of the processing. In addition to the development of the theoretical queueing model, experiments have been conducted with a multiprocessor system programmed as a compelled-signalling exchange, and the results compared with the theoretical predictions in order to validate the model.