DocumentCode
938515
Title
Delay estimate in a capacitively loaded URC line
Author
Zurada, J.M. ; Liu, T.
Author_Institution
University of Louisville, Speed Scientific School, Electrical Engineering Department, Louisville, USA
Volume
134
Issue
5
fYear
1987
fDate
10/1/1987 12:00:00 AM
Firstpage
243
Lastpage
245
Abstract
An approximated solution for the delay time of an open-ended uniformly distributed RC (URC) line has been developed. An estimate of the delay time for a capacitively loaded URC line has been derived. The results obtained may be useful for delay simulation in VLSI interconnections.
Keywords
delay lines; distributed parameter networks; linear network analysis; VLSI interconnections; capacitively loaded; delay simulation; delay time; open-ended; uniformly distributed RC line;
fLanguage
English
Journal_Title
Electronic Circuits and Systems, IEE Proceedings G
Publisher
iet
ISSN
0143-7089
Type
jour
DOI
10.1049/ip-g-1:19870037
Filename
4647145
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