• DocumentCode
    943181
  • Title

    Wirelength minimization for min-cut placements via placement feedback

  • Author

    Kahng, Andrew B. ; Reda, Sherief

  • Author_Institution
    Depts. of Comput. Sci. & Eng., Univ. of California, La Jolla, CA
  • Volume
    25
  • Issue
    7
  • fYear
    2006
  • fDate
    7/1/2006 12:00:00 AM
  • Firstpage
    1301
  • Lastpage
    1312
  • Abstract
    The advent of strong multilevel partitioners has made top-down min-cut placers a favored choice for modern placer implementations. Terminal propagation is an important step in min-cut placers because it translates partitioning results into global-placement wirelength assumptions. In this work, the repartitioning problem is carefully reexamined (Proc. ACM/IEEE Int. Symp. Physical Design, p. 18, 1997) in the context of terminal propagation and studied in an in-depth manner. Abstractly, it was observed that in repartitioning, future cell locations are used for present terminal propagations and that this can be conceptually regarded as a form of placement feedback. This concept was utilized to achieve accurate terminal propagation via feedback iteration and controller insertion to fine-tune the feedback response. This yields substantial reductions in placement wirelength. Implementing our approach in Capo [version 8.7 (Proc. ACM/IEEE Design Automation Conf., p. 477, 2000 and GSRC Bookshelf)] and applying it to standard benchmark circuits yields up to 14% wirelength reductions for the IBM benchmarks with an average improvement of 5.5% and up to 10% reductions for the Peko benchmarks with an average improvement of 5.37%. Experiments also show consistent improvements for routed wirelength, yielding up to 9% wirelength reductions and 5.8% average reduction with acceptable increase in placement runtime. In practice, the method proposed significantly improves routability without building congestion maps and also reduces the number of vias
  • Keywords
    VLSI; circuit feedback; circuit layout CAD; integrated circuit layout; logic CAD; logic partitioning; minimisation; multivalued logic; VLSI placement; controller insertion; feedback iteration; feedback response; min-cut partitioning; min-cut placements; placement feedback; placement runtime; repartitioning problem; routed wirelength; terminal propagation; wirelength minimization; wirelength reductions; Automatic control; Availability; Circuits; Computer science; Design automation; Feedback; Minimization; Routing; Runtime; Very large scale integration; Min-cut partitioning; VLSI placement; routing; terminal propagation;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2005.855917
  • Filename
    1634626