Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs

Author

Min, Kyeong-Sik ; Hun-Dae Choi ; Choi, Hun-Dae ; Kawaguchi, Hiroshi ; Sakurai, Takayasu

Author_Institution

Sch. of Electr. Eng, Kookmin Univ., Seoul, South Korea

Volume

14

Issue

4

fYear

2006

fDate

4/1/2006 12:00:00 AM

Firstpage

430

Lastpage

435

Abstract

As a candidate for the clock-gating scheme, Zigzag Super Cut-off CMOS (ZSCCMOS) has been proposed to reduce not only the switching power but also the leakage power. Due to its fast wakeup nature, the ZSCCMOS can be best suited to the clock-gating scheme. The wakeup time of the ZSCCMOS is estimated to be 12 times faster than the conventional Super Cut-off CMOS (SCCMOS) in 70-nm process technology. From the measurement of wakeup time in 0.6-/spl mu/m technology, it is observed to be eight times faster than the conventional scheme. Layout area, power, and delay overhead of the ZSCCMOS are discussed and analyzed in this paper.

Keywords

CMOS digital integrated circuits; clocks; integrated circuit layout; large scale integration; 0.6 micron; 70 nm; LSI; delay overhead; layout area; leakage power reduction; leakage suppressed clock-gating circuit; switching power reduction; zigzag super cut-off CMOS; CMOS process; CMOS technology; Circuits; Clocks; Collaboration; Degradation; Delay; Large scale integration; Threshold voltage; Time measurement; Clock-gating circuit; Super Cut-off CMOS (SCCMOS); Zigzag Super Cut-off CMOS (ZSCCMOS); leakage suppression circuit; low-power circuit;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2006.874378

Filename

1637473