Efficient IP routing table VLSI design for multigigabit routers

In this paper, an Internet Protocol (IP) forwarding table very large-scale integration design is presented. The table lookup becomes a great bottleneck when multigigabit links are required in today´s network routers. Hence, we present a lookup scheme that can efficiently handle IP routing lookup, insertion, and deletion inside the forwarding table. By introducing memory reduction and the novel skip function, we have successfully reduced the required memory size to about 0.59 MB. The forwarding table hardware design was carried out using Verilog hardware description language. It can achieve one route lookup for every memory access using pipeline implementation. Timemill post-layout simulation results show that the chip can furnish approximately 30×10⁶ lookups/s, and thus it can support up to 30 Gbits/s link speed. In addition, our design can be easily scaled from IPv4 to IPv6.