• DocumentCode
    957006
  • Title

    Characterization of the Body Node in PD SOI MOSFETs Using Multiport VNA Measurements

  • Author

    Lederer, Dimitri ; Raskin, Jean-Pierre

  • Author_Institution
    Tyndall Nat. Inst., Cork
  • Volume
    54
  • Issue
    11
  • fYear
    2007
  • Firstpage
    3030
  • Lastpage
    3039
  • Abstract
    This paper describes, for the first time, how the use of multiport vector network analyzer measurements can be exploited to provide a full small-signal characterization of body-contacted partially depleted silicon-on-insulator (SOI) MOSFETs. By combining information that was obtained from both three-port (with one body connection) and four-port (with two body connections) devices, the method successfully determines the value of the body resistance and the intrinsic and extrinsic body capacitances in these devices for any given bias condition. A complete three-port model including the body node is therefore obtained and shown to closely match with ac measurements. The extraction technique is shown to be accurate, straightforward, and time effective, which makes it an ideal characterization tool, for instance, to parameterize compact models or investigate the quality of new SOI technologies.
  • Keywords
    MOSFET; network analysers; semiconductor device measurement; semiconductor device models; silicon-on-insulator; PD SOI MOSFET; body resistance; extrinsic body capacitances; four-port devices; intrinsic body capacitances; multiport VNA measurements; multiport vector network analyzer measurements; partially depleted silicon-on-insulator MOSFET; three-port devices; three-port model; Capacitance measurement; Contact resistance; Electrical resistance measurement; Energy consumption; Helium; Immune system; MOSFETs; Parasitic capacitance; Silicon on insulator technology; Time measurement; AC characterization; ac floating-body effects (FBEs); body capacitances; body contacts (BCs); body resistance; multiport measurements; multiport vector network analyzer (VNA); parasitics; partially depleted (PD); silicon-on-insulator (SOI) technology; small-signal modeling; three-port model;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2007.907188
  • Filename
    4367601