Submicrometer near-intrinsic thin-film SOI complementary MOSFETs

Two-dimensional numerical simulations indicate that a surface-potential bending greater than the Si-film Fermi potential is required to reach the threshold condition for the near-intrinsic thin-film SOI (silicon-on-insulator) MOSFETs. Additionally, both n- and p-type SOI films result in approximately the same device threshold voltage when in the near intrinsic state and fully depleted condition. The threshold voltages of these devices are mainly dependent on the work function of gate material. High-performance submicrometer near-intrinsic thin-film SOI complementary MOSFETs with balanced threshold voltages of about 0.4 V (negative for PMOSFETs) are achievable with proper selection of gate material and back-gate bias. For very thin (less than 100 nm) SOI films, drain-induced barrier lowering (DIBL) is not sufficient to cause degradation of the threshold voltage or punchthrough behavior in the submicrometer region. For relatively thick (greater than 100 nm) SOI films, DIBL becomes more pronounced but can be suppressed by a proper back-gate bias. The simulated front-gate linear transconductance remains nearly constant up to about 10¹⁵ cm^-3 and then falls off rapidly with increasing doping concentration because of mobility degradation. The subthreshold slope increases with decreasing drain voltage as a result of DIBL, but the increase is small for very thin SOI films.