Electron and hole charge separation with a dual channel transistor

Summary form only given. The authors have fabricated a n⁺ poly gate dual channel memory transistor with a 0.75- mu m-deep n-buried layer on <100> p-Si, and a triple dielectric (ONO) sandwich comprising a 20- mu A tunneling oxide, 115 AA of LPCVD (low-pressure chemical vapor deposition) deposited Si₃N₄, and 52 AA of top oxide. For positive gate bias beyond flat band, electrons are collected at the substrate. For negative gate bias beyond flat band, holes are supplied by the surface channel contacts and the electrons, spatially separated from the holes by the potential well in the buried channel, are collected at the buried-channel contacts. The data for electron and hole injection into the nitride show centroids (from the tunneling oxide-nitride interface) to be approximately equal to the nitride thickness for small level injection, decreasing with increasing injection and saturation beyond 1 mu C/cm². The saturation values for electron and hole centroids are 75+or-5 AA and 55+or-2 AA, respectively.