DocumentCode
958924
Title
A Note on Three-Valued Logic Simulation
Author
Breuer, Melvin A.
Author_Institution
Department of Electrical Engineering, University of Southern California, Los Angeles, Calif. 90007.
Issue
4
fYear
1972
fDate
4/1/1972 12:00:00 AM
Firstpage
399
Lastpage
402
Abstract
In this note we discuss a few attributes and pitfalls of three-valued (0, 1, u) digital logic simulation. The areas covered include hazard and race detection, fault detection, verifying the reset logic of a machine, and the problems encountered with self-timing circuits and in employing a complement for u.
Keywords
Circuit simulation; Delay effects; Delay systems; Electrical fault detection; Fault detection; Hazards; Latches; Logic circuits; Steady-state; Wires; Fault detection; hazards; multivalue simulation; races; self-timing circuits; simulation;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1972.5008985
Filename
5008985
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