• DocumentCode
    960157
  • Title

    Sea-of-leads MEMS I/O interconnects for low-k IC packaging

  • Author

    Dang, Bing ; Bakir, Muhannad S. ; Patel, Chirag S. ; Thacker, Hiren D. ; Meindl, James D.

  • Author_Institution
    Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
  • Volume
    15
  • Issue
    3
  • fYear
    2006
  • fDate
    6/1/2006 12:00:00 AM
  • Firstpage
    523
  • Lastpage
    530
  • Abstract
    Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.
  • Keywords
    integrated circuit interconnections; integrated circuit packaging; micromechanical devices; printed circuits; silicon; system-on-chip; Cu; IC chips; MEMS I/O interconnects; PWB substrate; Si chip; coefficient of thermal expansion; composite substrate; interlayer dielectrics; low stress connection; low-k IC packaging; mechanical compliance; sea of leads; wafer level packaging; Assembly; Dielectric substrates; Failure analysis; Integrated circuit packaging; Lead; Micromechanical devices; Soldering; Springs; Thermal expansion; Wafer scale integration; Low-k interlayer dielectrics; microelectromechanical systems (MEMS) I/O interconnects; solder joints; underfill;
  • fLanguage
    English
  • Journal_Title
    Microelectromechanical Systems, Journal of
  • Publisher
    ieee
  • ISSN
    1057-7157
  • Type

    jour

  • DOI
    10.1109/JMEMS.2006.876792
  • Filename
    1638478