DocumentCode
962304
Title
A Testable PLA Design with Low Overhead and High Fault Coverage
Author
Khakbaz, Javad
Author_Institution
Center for Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA 94305.; Memorex Corporation, Santa Clara, CA.
Issue
8
fYear
1984
Firstpage
743
Lastpage
745
Abstract
A new design of testable PLA´s is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it has very high fault coverage (all single and multiple stuck-at faults, crosspoint faults, and all combinations thereof are detected); and it can be used for designing testable folded PLA´s. This design, however, is not appropriate for built-in test.
Keywords
Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Fault tolerance; Hardware; Logic circuits; Logic testing; Programmable logic arrays; PLA folding; programmable logic array; testing;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1984.5009362
Filename
5009362
Link To Document