Designing Systolic Algorithms Using Sequential Machines

We present a tool that is useful in the design and analysis of systolic systems. Specifically, we give characterizations of systolic arrays in terms of (single processor) sequential machines which are easier to program and to analyze. We give several examples to illustrate the utility of the design tool. In particular, we show how systolic designs for such problems as integer bitwise multiplication, dynamic programming, and language recognition can easily be derived using the characterizations. We also present some new results concerning the properties and computational power of systolic arrays which can be obtained using the characterizations.