A Characterization of Ternary Simulation of Gate Networks

Ternary simulation techniques provide efficient methods for the analysis of the behavior of VLSI circuits. However, the results of ternary simulation have not been completely characterized. In this paper we prove a somewhat modified version of the Brzozowski-Yoeli conjecture (stated in 1976) that the results of the ternary simulation of a gate network N correspond to the results of the binary race analysis of Ñ in the ``multiple-winner´´ model, where Ñ is the network N in which a delay has been inserted in each wire.