Critical area and critical levels calculation in IC yield modeling

A method is described for calculating critical coefficients to be included in an IC yield model for each masking step. The yield model is a function of the chip surface, the defect density, and a mathematical law. The method relies on partitioning total mask area at each level into area subcomponents sensitive to a minimal defect size using a design rule checker program. Defect density with respect to size has been experimentally determined, and the selected mathematical law corresponded to the data. Yield per level Y_i was determined by applying the model to critical areas with their corresponding defect densities. The calculation of α_i has been carried out using the equation Y_i=1/(1+A_Tλ^α i) where Y_i is the i-level yield, A_T the total chip area, and λ the average value of defect density per level. It has been found that the resultant α_i values are stable in a given environment whatever the technology, the average defect density value, and the design rules