A voltage-controllable linear MOS transconductor using bias offset technique

Author

Wang, Zhenhua ; GuggenbÜhl, Walter

Author_Institution

Dept. of Electr. Eng., Swiss Federal Inst. of Technol., Zurich, Switzerland

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

315

Lastpage

317

Abstract

A linear large-signal MOS transconductor with the gain adjustable linearly by a voltage is described. A perfect linear transfer characteristic is obtained by two cross-coupled differential transistor pairs operating in saturation pairwise at unequal bias, offering offset-free operation, with both differential or single-ended input and differential output. Single-ended output is achievable by use of a current mirror. The nonlinearity caused by mobility reduction, channel-length modulation, mismatch, etc. is discussed. A test circuit with transconductance of 6.25 μmho has been built with 3-μm MOS components, and a linearity error of less than ±1% was measured for an input voltage range from -4 to 4 V

Keywords

MOS integrated circuits; active networks; linear integrated circuits; -4 to 4 V; 3 micron; 6.25×10^-6 mho; bias offset technique; channel-length modulation; cross-coupled differential transistor pairs; current mirror; differential input; differential output; gain adjustment; large signal type; linear MOS transconductor; linear transfer characteristic; mismatch; mobility reduction; monolithic IC; offset-free operation; single-ended input; transconductance; Area measurement; Circuit testing; Integrated circuit measurements; Integrated circuit testing; Linearity; Mirrors; Threshold voltage; Transconductance; Transconductors; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50321

Filename

50321