DocumentCode
980151
Title
A fast-settling 3 V CMOS buffer amplifier
Author
Gradinariu, Iulian ; Gontrand, Christian
Author_Institution
Lab. de Phys. de la Matiere, INSA de Lyon, Villeurbanne, France
Volume
43
Issue
6
fYear
1996
fDate
6/1/1996 12:00:00 AM
Firstpage
433
Lastpage
437
Abstract
This paper presents a two-stage fast, power-efficient 3 V CMOS buffer amplifier with rail-to-rail input/output voltage ranges. Because of its constant gm, class-AB input stage, the amplifier is free of slew-rate limitation and its settling-time is quasi-independent on input step amplitude. The amplifier has 6 MHz unity-gain frequency, 1 mW power-consumption and settles to 1% accuracy within 180 ns on 100 pF load. As the class-AB input stage operates at constant quiescent current over the input voltage range, CMRR exceeds 70 dB
Keywords
CMOS analogue integrated circuits; buffer circuits; operational amplifiers; 1 mW; 180 ns; 3 V; 6 GHz; CMRR; class-AB input stage; low-voltage circuit; power efficiency; rail-to-rail voltage range; settling time; slew rate; transconductance; two-stage CMOS buffer amplifier; Coupling circuits; Frequency; Helium; MOS devices; Power amplifiers; Rail to rail amplifiers; Rail to rail inputs; Rail to rail operation; Very large scale integration; Voltage;
fLanguage
English
Journal_Title
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
Publisher
ieee
ISSN
1057-7122
Type
jour
DOI
10.1109/81.503251
Filename
503251
Link To Document