Cellular logic bus arbitration

The functional and VLSI design of a novel one-of-N bus arbitration circuit for a time-shared bus-interconnected multiprocessor system is presented. The proposed system is a multilevel, hierarchical, two-bit cellular processor structure. The arbitration protocol of rotating priority has been customised to produce a hierarchical, fairness-oriented, rotating-priority protocol that guarantees efficient and deadlock-free time sharing of the bus, with better complexity measures compared to both rotating- and unequal-priority protocols.