Power dissipation models and performance improvement techniques for CMOS inverters with RC line and tree interconnections

Physical power dissipation models of CMOS inverters with RC line and tree interconnection networks are presented. Compared to SPICE simulation results, the maximum error in the model calculated results using the models is 12% for power dissipation in CMOS inverters with different RC values in each branch of the tree networks, different gate sizes, device parameters, and even input excitation waveforms not deviating much from the characteristic waveforms. Based upon the mathematical optimisation method, as well as on the developed power dissipation models and the delay models, an experimental sizing program is also constructed for improving various circuit performances such as delay time, power-delay product, and delay time with fixed power dissipation specifications. In this program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one improvement technique and determine the suitable sizes and/or number of drivers/repeaters for optimal circuit performance. It is found from the sizing results of the experimental CAD program that the required tapering factor for minimum power-delay product in cascaded drivers of interconnection lines or trees is in the range 2-6 instead of 4-8 for a minimum delay