DocumentCode
988681
Title
Accurate computation of field reject ratio based on fault latency
Author
Das, Dharamvir ; Seth, Sharad C. ; Agrawal, Vishwani D.
Author_Institution
Cadence Design Systems, Noida, India
Volume
1
Issue
4
fYear
1993
Firstpage
537
Lastpage
545
Abstract
It is shown that the known methods of field reject ratio prediction are not accurate since they fail to realistically model the process of testing. The authors model the detection of a fault by an input test vector as a random event. However, the detection of a fault may be delayed for various reasons: the fault may be detectable only by application of a sequence of vectors or it may not have been targeted until later. In the statistical model, a fault is characterized by two parameters: a per-vector detection probability and an integer-valued latency. Irrespective of the detection probability, the fault cannot be detected by a vector sequence shorter than its latency. The circuit is characterized by the joint distribution of latency and detection probability over all faults. This distribution, obtained by applying the Bayes´ rule to the actual test data, allows computations the field reject ratio. The sensitivity of this approach to variations in the measured parameters is also investigated.<>
Keywords
VLSI; failure analysis; fault location; integrated circuit testing; integrated logic circuits; logic testing; probability; Bayes´ rule; VLSI chips; fault detection; fault latency; field reject ratio; input test vector; integer-valued latency; joint distribution; per-vector detection probability; statistical model; testing; vector sequence; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Delay; Electrical fault detection; Fault detection; Probability; Semiconductor device measurement; Very large scale integration;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.250201
Filename
250201
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