• DocumentCode
    992970
  • Title

    Defocus-Aware Leakage Estimation and Control

  • Author

    Kahng, Andrew B. ; Muddu, Swamy ; Sharma, Puneet

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Univ. of California at San Diego, La Jolla, CA
  • Volume
    27
  • Issue
    2
  • fYear
    2008
  • Firstpage
    230
  • Lastpage
    240
  • Abstract
    Leakage power is one of the most critical issues for ultradeep submicrometer technology. Subthreshold leakage depends nearly exponentially on linewidth, and consequently, variation in linewidth translates to a large leakage variation. A significant fraction of variation in the linewidth occurs due to systematic variations involving focus and pitch. In this paper, we propose a new leakage-estimation methodology that accounts for focus-dependent variation in the linewidth. Our approach computes the pitch of each device in the design and uses it along with defocus information to predict the linewidth of the device. Once the linewidths of the devices in a cell are calculated, the cell leakage is computed to be the sum of leakages of all off-devices in the cell; device leakages are found from a linewidth-leakage table that is precharacterized with SPICE simulations. The presented methodology significantly improves the leakage estimation and can be used in existing leakage-reduction techniques to improve their efficacy. To demonstrate the use of our approach for leakage reduction, we modify the previously proposed linewidth-biasing technique of Gupta to consider the systematic variations in linewidth and further optimize the leakage power. Our method reduces the leakage spread between worst and best process corners by up to 62% compared with the conventional corner-based analysis. Defocus awareness improves the leakage reduction from linewidth-biasing by up to 7%.
  • Keywords
    electrical faults; nanotechnology; SPICE simulations; defocus-aware leakage estimation; leakage control; subthreshold leakage; ultradeep submicrometer technology; Computational modeling; Gate leakage; High-K gate dielectrics; Lithography; MOS devices; Predictive models; SPICE; Subthreshold current; Temperature; Threshold voltage; Estimation; leakage power; lithography; optimization; topography;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2007.913387
  • Filename
    4391073