DocumentCode
997373
Title
Very-high-frequency CMOS analogue buffer
Author
Xu, Peng ; Schaumann, R.
Author_Institution
Dept. of Electr. Eng., Portland State Univ., OR, USA
Volume
29
Issue
16
fYear
1993
Firstpage
1458
Lastpage
1460
Abstract
A simple CMOS on-chip differential buffer is presented. From simulations based on a 2 mu m n-well CMOS process this buffer can give a 260 MHz cutoff frequency with a load of 50 k Omega paralleled by 1 pF. THD at 1 MHz for 1 V peak to peak is as low as 0.003%. Offset voltage is only a few millivolts even if considering mismatch among the transistors. The circuit is very useful as a high-speed internal node buffer or test/pin drive buffer. The power supply can be as low as +or-2.5V.
Keywords
CMOS integrated circuits; buffer circuits; linear integrated circuits; 2 micron; 260 MHz; CMOS analogue buffer; THD; cutoff frequency; differential buffer; internal node buffer; mismatch; n-well CMOS process; test/pin drive buffer;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19930976
Filename
252494
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